This invention relates to an exposure method utilizing an energy beam, such as an electron beam, for drawing a chip pattern on a substrate. More specifically, this invention relates to an exposure method incorporating a simplified process to scale a pattern for providing magnification or reduction of the pattern's size.
Recently, a method for manufacturing high integrated semiconductor devices has been widely employed whereby a reticle pattern drawn on a substrate by an electron beam exposure device is projected onto a semiconductor wafer by utilizing an optical size-reducing projector. The projecting process is repeated until a plurality of chips are formed on the wafer, each chip contiguously positioned with respect to its adjacent chips. To improve wafer yield, it is necessary to reduce the area of each chip in order to permit as many LSI chips as possible to be cut from the wafer. Consequently, LSI chips can be produced which are multiples (e.g., 1, 0.9, 0.8) of original pattern; the smallest multiple which performs properly is then selected as the mask pattern used for actual production. In producing reticles at different magnifications such as 1.times., 0.9.times. or 0.8.times. etc., (hereinafter called scaling factor .alpha.), each different reticle is required to have alignment marks of the same size. Since the size and position of these alignment marks are unique for the particular optical reduction projector used, they must have the same size and position despite the use of different scaling factors. The conventional method separates the drawing of the chip pattern from the drawing of the alignment marks. This conventional method involves manufacturing a scaled reticle, having a given scaling factor .alpha., from original pattern data in accordance with the following steps (1)-(3):
(1) The drawing parameters of the electron beam exposure device are converted by the desired scaling factor .alpha.. That is, the diameter d of the electron beam is adjusted to be .alpha.d; the deflection amplitude a of the electron beam is adjusted to be .alpha.a; the beam scan interval i is adjusted to be .alpha.i; a frequency division factor m is selected to be approximately equal to .alpha.nd/.lambda., where .lambda. is a wavelength of laser light emitted by a laser interfermeter for measuring the x-y table displacement and n is an integer; and x-y table displacement velocity v is adjusted to be .alpha.v; PA1 (2) A chip pattern is drawn on the reticle with chip pattern data; PA1 (3) The electron beam diameter d, deflection amplitude a, beam scan interval i, frequency division factor m and x-y table displacement velocity v are then re-adjusted with the scaling factor equal to 1, and the alignment mark pattern is finally drawn. This necessary re-adjustment of the parameters during the middle of the drawing cycle, however, adversely effects the accuracy of the drawn patterns. Moreover, this additional procedure is time-consuming and will effect the output yield.